四位二进制加法器是由两个二位二进制加法器组成的吗
我乱的不行了,弄不清
原理图由一个半加器和三个全加器组成。VHDL程序相对比较简单。LIBRARY ieee;USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; ENTITY adder4bit ISPORT(a,b : IN std_logic_vector(3 downto 0); s : out std_logic_vector(3 downto 0); --sum co : OUT std_logic); --carry outEND adder4bit;ARCHITECTURE a OF adder4bit ISSIGNAL temp:std_logic_vector(4 downto 0);BEGINtemp<=a+b;co<=temp(4); s<=temp(3 downto 0);END
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